Cadence Palladium Z1 enterprise emulation platform enables GUC to accelerate SoC design; performs complex SoC verification tests



Cadence Design Systems announced that Global Unichip Corp. (GUC) has adopted the Cadence Palladium Z1 Enterprise Emulation Platform to accelerate system-on-chip (SoC) design and drive innovation in the semiconductor industry. By combining the Palladium Z1 emulation platform with Cadence Xcelium Parallel Logic Simulation, GUC engineers were able to apply more complex SoC verification test scenarios with full debug visibility, accelerating verification by up to 795 times.

The Palladium Z1 emulation platform allowed GUC to improve system-on-silicon verification and optimize hardware and software integration earlier in the verification process, ensuring high reliability. The compile capabilities included with the Palladium Z1 emulation platform also enabled GUC to achieve more predictable turnaround times for full-chip emulation model builds. This helped GUC engineers to debug quickly and explore design changes 20 times faster, which was not feasible with other design methodologies.

In addition to using the Palladium Z1 emulation platform and Xcelium Parallel Logic Simulation, GUC also used other solutions in the Cadence Verification Suite including Verification IP (VIP) and the JasperGold Formal Verification Platform. The broader Cadence Verification Suite provided GUC with automation, debug, tracking, management and measurement of verification tasks across verification flows and engines, which improved productivity and team collaboration.

The Palladium Z1 emulation platform enabled congruency with the adjacent verification suite engines, allowing GUC to significantly optimize overall verification productivity, which ultimately led to improved product quality.

The Palladium Z1 Enterprise Emulation Platform is part of the Cadence Verification Suite. It supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of JasperGold, Xcelium, Palladium Z1 and Protium S1 core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

The way that the Palladium Z1 platform manages emulation resources can save you time and effort. The platform’s unique virtual target relocation capability, along with advanced job shaping allocation, avoids recompiles by allowing payloads to be allocated into available resources at runtime. The platform can execute up to 2304 parallel jobs with 4 million gate granularity and scales to 9.2 billion gates.

Compared to the Palladium XP II environment, the new platform offers up to 44 percent reduction in power density, along with a reduction in power consumption per emulation cycle by a factor of three or more. The power advantages are a result of an average of 2.5 times better system utilization and number of parallel users; up to five times better emulation throughput; up to 140MG per hour compile times; and comes with superior debug depth and upload speeds.

Its rack-based blade architecture results in a 92 percent smaller footprint and 8X better gate density, compared to the Palladium XP II platform. The Palladium Z1 processor-based compute engine is also designed with massive parallelism, delivering four times better user granularity than its nearest competitor.

“A high-performance ASIC verification solution is vital for driving our product innovations and business, and we need to continually strive to improve our overall product quality,” said Dr. Ken Chen, president at Global Unichip Corporation. “After comparing alternative solutions in the market, we selected Cadence’s Palladium Z1 Enterprise Emulation Platform for its effectiveness in ASIC verification productivity and use-model versatility. Adopting the Palladium Z1 emulation platform in conjunction with Xcelium Parallel Logic Simulation and the broader Cadence Verification Suite has enabled us to deliver flexible ASIC services that elevate our visionary IC customers to the next level of leadership in their respective markets.”

 

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